The present invention relates to memory devices generally and, more particularly, to a configurable memory for programmable logic devices.
Traditionally there are two types of programmable logic architectures: complex programmable logic device (CPLDs) and field programmable gate arrays (FPGAs). The CPLD can be constructed as a one-dimensional array of logic blocks made of 16 macrocells and a product term array connected through a single central interconnect scheme. The CPLD achieves high performance by being able to complete a complex logic function in a single pass of the logic array, and has predictable timing by having every output or I/O pin connected to every logic block input through a central interconnect structure. The CPLD can be non-volatile by using an EEPROM process. However, the CPLD has no available on-chip RAM.
An FPGA architecture is constructed from a two dimensional array of logic blocks called CLBs. The CLBs are made from 4-input look-up-tables (LUTs) and flip-flops. The LUTs can be used as distributed memory blocks. The CLBs are connected by a segmented interconnect structure. The FPGA architecture supports a low standby power and the LUTs can use a simple logic CMOS process. Since the two-dimensional array of CLBs and the segmented interconnect structure are scalable, an FPGA can achieve high density. However, a dual port or FIFO memory is slow and inefficient to implement with LUTs.
The present invention concerns an apparatus comprising a memory device and a programmable logic device. The memory device may be configured to (i) connect to a first bus and a second bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate the control signals.
The objects, features and advantages of the present invention include providing an architecture, circuit and/or method for a configurable memory that may (i) provide a configurable single port RAM, dual port RAM and/or FIFO, (ii) provide dedicated dual port memory logic and arbitration, and FIFO memory logic and flags that may improve memory performance, (iii) be placed in the routing channels of a programmable logic device to achieve higher performance with I/O blocks, (iv) be cascadable with other configurable memory blocks to form larger block sizes and/or (v) be used as synchronous or asynchronous memory.